Hybrid dielectric non-volatile memory with nano particles (Si/SiO2 core/shell) as charge trapping layer

ABSTRACT

Si/SiO 2  core/shell nanostructures with sizes below 30 nm as trapping points in UV curable hybrid organic-inorganic gate dielectrics are presented in order to investigate printable nano floating gate transistors. Not only does the novelty of this invention comes from fabricating high-quality hybrid organic/inorganic gate dielectric layer by Sol-Gel process at low temperature but also incorporating the monolayer of high-density of Si nanoparticles (NPs) without obvious interface defects and keeping the quality of dielectric layers. Fixed-charge trapping defects are successfully removed from hybrid dielectrics by UV curing together with low temperature thermal curing and mobile charges solely related to Si/SiO 2  core/shell nanostructures on charge trapping layer clearly demonstrate memory effects on printable device. Thin/uniform SiO 2  shell on each Si NP functions as tunneling layer of flash memory devices, significantly simplifying the fabrication of printable nano floating gate memory device.

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FIELD OF THE INVENTION

The present invention relates to a printable non-volatile memory, andparticularly relates to a method for preparing hybrid organic-inorganicdielectric layers for flash memory transistors by solution process atlow temperature, and more particularly relates to a method forfabricating a non-volatile memory with nano particles as charge trappinglayer.

BACKGROUND

The following references are cited in the specification. Disclosures ofthese references are incorporated herein by reference in their entirety.

LIST OF REFERENCES

-   [1]. Y. J. Park et al., IEEE Trans on Dielectrics and Electrical    Insulation 17(4), 1135-1163 (2010)-   [2]. Introduction to Flash Memory, PROCEEDINGS OF THE IEEE 91(4),    APRIL 2003 [3]. Kim et al., Appl. Phys. Lett. 96, 033302 (2010)-   [4]. T. Sekitani, Science 326, 1516-1519 (2009)-   [5]. C. C. Leu, S. T. Chen, F. K. Liu and C. X. Wu, J. Mater. Chem.    22, 2089-2098 (2012)-   [6]. B. Chandar Shekar, Jiyeon Lee and Shi-Woo Rhee, Korean J. Chem.    Eng., 21(1), 267-285 (2004)-   [7]. C. Z. Zhao et al., IEEE TRANSACTIONS ON ELECTRON DEVICES 55(7),    1647-1656 (2008)-   [8]. June Whan Choi, Ho Gyu Yoon, Jai Kyeong Kim, Organic    Electronics 11, 1145-1148 (2010)-   [9]. Jin-Yong Lee et al., Appl. Phys. Lett. 104, 093514 (2014)

Electronic devices are traditionally fabricated using rigidsemiconductors and high-temperature manufacturing method. In contrast,printed devices can be processed at low temperatures and on large-areapolymeric substrates. Data storage is one key requirement in manyelectronic devices. Plenty of efforts have been spent on printed memorydevices in order to realize large-area, flexible, and low-costelectronic devices. For example, ferroelectric (Fe) polymer,P(VDF-TrFE), was developed for electrical switching [1]. The electricalswitching of Fe polymers, P(VDF-TrFE), requires a relatively largecoercive field of ˜MV/cm with thickness down to 100 nm, and the coercivefield required to reverse the macroscopic polarization increases withdecreasing film thickness. Thus, it is difficult to obtain large enoughmemory window with program and erase voltages below 20V, which ischallenging printed memories for low-power applications. Therefore,these memory transistors based on Fe polymer are not compatible withcommercial reading systems which operate under low power and low voltage[2].

In order to make nonvolatile memory transistors operated under lowvoltage (<10V) and be printable on flexible substrates, floating gatethin film transistors are developed with dielectric gate layer thinenough [3,4]. The charge leakage from the Au NPs (nano particles)floating gate can be suppressed by improving the NPs/dielectricinterface with Au NPs spin-coated on 3-aminopropyltrimethoxysilane(APTMS)-modified SiO₂. Furthermore, a simple but effective self-assemblymonolayer (SAM) method was used to construct an Au—SiO₂ core-shell NCcapacitor by use of APTMS as a mediator [5]. But the process temperaturefor this memory device is higher than 400° C. and then this device isnot able to be fabricated by printing techniques.

The significance of dielectric layer is attracting more and moreinterests in order to develop high-performance printable floating gatememory transistors. Many studies have tried to find better gatedielectrics with polymeric materials, inorganic/organic hybrids,inorganic/organic bilayers, and organic/inorganic hybrids via sol-gelreaction. In the case of a polymer dielectric film, one of the drawbacksis the high operating voltage in devices due to its thickness and lowdielectric constant (PMMA 2.5-4.5, polyimide 2.6-3.3, Teflon 1.9),compared with inorganic dielectrics (Al₂O₃ 9 and Ta₂O₅ 26) [6]. To solvethis problem, high-k inorganic materials such as Al₂O₃ and Ta₂O₅ hadbeen used as gate insulators due to their dielectric constants which aremuch higher than those of polymers. But metal oxide has relatively highleakage current and these films can be produced with the vacuumtechniques, such as chemical vapor deposition, sputtering or flamehydrolysis. Vacuum equipment is not suitable for a low temperature andlow cost process required by printing techniques. Alternatively, high-kinorganic nanoparticles can be dispersed in polymer matrix. However, ananocomposite dielectric layer with high-k NPs embedded in polymermatrix has a rough surface and high gate leakage current to have a lowon/off current ratio. In addition, it is difficult to eliminatefixed-charge trapping defects generated by high-k NPs in dielectriclayer. These fixed-charge associated trapping defects in dielectricswill become deadly shielding of preventing the mobilecharging/discharging progress in memory transistors. The sol-gel derivedsiloxane based organic-inorganic hybrid materials (hybrimers) arenanocomposite materials in which inorganic and organic components areintimately linked at molecular scale by a covalent bond and nano-sizedoligomers are well-dispersed. Since they combine the characteristics ofboth glass and polymers, it has low leakage current density and haspotential chances of removing fixed-charge trapping defects in hybridorganic-inorganic dielectrics.

However, the memory behaviour and the production cost of theconventional technologies still fail to meet the need of the market.

Consequently, there is an unmet need to have a method for fabricatingnonvolatile memory transistors being applicable for printed electronicswith desirable memory behavior and low production cost.

SUMMARY OF THE INVENTION

To satisfy the requirements of manipulating the trap levels and trapsites for floating gate transistors, employment on nano-crystalsfloating gate is considered to be an alternative approach to replace thetraditional planar floating gate for information storage. The presentinvention has focused on incorporating Si NPs as the charge storageelements in non-volatile memory devices. Nanoparticle-based memoriesbenefit from reduced lateral discharge paths, and promise largerretention time, lower power consumption, and faster operation. Comparedto metal NPs (Au, Ag, Al, etc.), applying Si nanocrystals as floatinggate can remove metal contaminations in gate dielectrics, which iscritical to reduce device leakage.

In the present invention, Si/SiO₂ core/shell nanostructures are used towork as trapping sites in floating gate memory. Uniform SiO₂ shell of 3nm to 5 nm in thickness surrounding each Si NPs is formed by siliconcores simultaneously oxidized in solutions and it reduces lateraldischarging with retention properties improved. More importantly, withmonolayer of Si NPs trapping layers, this ultrathin/uniform SiO₂ shellfunctions as tunneling layer of flash memory devices and leads to quitelow operation voltage for printable NPs floating-gate memory devices.Compared to traditional memory stacks (substrate/tunnel layer/chargetrapping layer/control layer/gate electrode) [2, 3, 4 5], the presentinvention didn't involve separate tunnel layer, and the high-qualitySiO₂ shell acts as tunnel layer.

Also hybrid organic/inorganic dielectrics layer is prepared by sol-gelmethod. With sol-gel formula optimized and curing conditions improved atlow temperature, memory devices with this novel hybrid dielectrics showrelatively low leakage current density and more importantly it issuccessful to remove fixed-charge associated trapping defects indielectrics.

Accordingly, a first aspect of the presently claimed invention is toprovide a printable floating gate transistor for non-volatile memory.

According to an embodiment of the presently claimed invention, afloating gate memory device comprises: a substrate; a charge trappinglayer formed on the substrate, wherein the charge trapping layercomprises a hybrid organic/inorganic dielectric material andsilicon/silicon dioxide (Si/SiO₂) core/shell nanostructures, and theSi/SiO₂ core/shell nanostructures are embedded within the hybridorganic/inorganic dielectric material; a hybrid organic/inorganicdielectric layer formed on the charge trapping layer; and a gateelectrode formed on the hybrid organic/inorganic layer; and wherein eachof the Si/SiO₂ core/shell nanostructures comprises a Si core enclosed bya SiO₂ shell acting as a tunnel layer for the floating gate memorydevice.

A second aspect of the presently claimed invention is to provide amethod for fabricating a floating gate transistor.

According to an embodiment of the presently claimed invention, a methodfor fabricating a floating gate memory device comprises: providing asubstrate; mixing silicon particles with a solution comprising anorganic solvent and hydrogen peroxide to form a silicon/silicon dioxide(Si/SiO₂) core/shell nanostructures solution, wherein the siliconparticles comprises a size of 10 nm to 50 nm; coating the Si/SiO₂core/shell nanostructure solution on the substrate; drying the Si/SiO₂core/shell nanostructure solution with a drying temperature in a rangeof 60° C. to 150° C. to form a charge trapping layer; mixing3-methacryloxypropyltrimethoxysilane (MEMO), zirconium propoxide (ZrPO),methacrylic acid (MAA), and a photoinitiator to form a hybridorganic/inorganic dielectric solution, coating the hybridorganic/inorganic dielectric solution on the charge trapping layer;curing the hybrid organic-inorganic dielectric solution on the chargetrapping layer by UV light; curing the hybrid organic/inorganicdielectric solution thermally with a curing temperature in a range of130° C. to 180° C. to form a hybrid organic/inorganic layer; and forminga gate electrode on the hybrid organic/inorganic layer.

The sol-gel derived organic-inorganic hybrid materials of the dielectriclayer are nano-composite materials in which inorganic and organiccomponents are intimately linked at the molecular scale by a covalentbond and nano-sized oligomers are well dispersed. The trap sites of thecharge trapping layer directly relate to memory window which can becontrolled by varying the density of nanoparticles. The memorytransistor of the present invention exhibits a memory window of 4.2 V,long retention time (100 ks) with low operating voltage (<7 V).

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are described in more detailhereinafter with reference to the drawings, in which:

FIG. 1A shows a schematic diagram of a printable floating gatenon-volatile memory device with Si/SiO₂ core/shell structures as chargetrapping layer according to an embodiment of the presently claimedinvention;

FIG. 1B shows a schematic structure of a traditional floating gatenon-volatile memory device in a prior art;

FIG. 2 shows a flow chart of a method for fabricating a non-volatilememory device according to an embodiment of the presently claimedinvention;

FIG. 3 is a graph showing leakage current density at different biasfields according to an embodiment of the presently claimed invention;

FIG. 4 is a flowchart showing process flow for preparing a hybridSol-Gel solution according to an embodiment of the presently claimedinvention;

FIG. 5A is an atomic force microscopy AFM image of monolayer Si/SiO₂core/shell structures coating according to an embodiment of thepresently claimed invention;

FIG. 5B is a TEM image of Si/SiO₂ core/shell structures with shellthickness of ˜5 nm according to an embodiment of the presently claimedinvention;

FIG. 6 is a graph showing memory effects of Si/SiO₂ core/shellstructures according to an embodiment of the presently claimedinvention;

FIG. 7A is a graph showing memory behavior tuned via varying the voltagestress time according to an embodiment of the presently claimedinvention;

FIG. 7B is a graph showing memory behavior tuned via varying the stressvoltage amplitude according to an embodiment of the presently claimedinvention;

FIG. 8 is a graph showing retention properties of memory based onSi/SiO₂ core/shell NPs according to an embodiment of the presentlyclaimed invention; and

FIGS. 9A-D are CV loops measured under different voltage stress time forsamples 1, 2, 3, and 4 respectively according to an embodiment of thepresently claimed invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following description, a memory device, and the correspondingembodiments of the fabrication methods are set forth as preferredexamples. It will be apparent to those skilled in the art thatmodifications, including additions and/or substitutions, may be madewithout departing from the scope and spirit of the invention. Specificdetails may be omitted so as not to obscure the invention; however, thedisclosure is written to enable one skilled in the art to practice theteachings herein without undue experimentation.

Si/SiO₂ core/shell nanostructures with sizes below 30 nm as trappingpoints in UV curable hybrid organic-inorganic gate dielectrics arepresented in the present invention. Not only does the novelty of thepresent invention comes from fabricating high-quality hybridorganic/inorganic gate dielectric stacks by Sol-Gel process at lowtemperature but also incorporating the monolayer of high-density of Sinanoparticles (NPs) without obvious interface defects and keeping thehigh-quality of dielectric layers. In the present memory devicesfabricated by solution process at low temperature, fixed-charge trappingpoints associated with as synthesized defects are successfully removedfrom dielectric layer and clear memory effects are demonstrated withtrapping functions solely related to Si/SiO₂ core/shell nanostructures.

As shown in FIG. 1A, a floating gate transistor 100 of the presentinvention comprises a Si substrate 101, a charge trapping comprising aplurality of Si/SiO₂ core/shell nanostructures 105 embedded within ahybrid organic/inorganic dielectric material 106, a hybridorganic/inorganic dielectric layer 103, and a gate electrode 104. Thecharge trapping layer 102 is formed on the Si substrate 101. The hybridorganic/inorganic dielectric layer 103, acting as a control layer formemory device, is formed on the charge trapping layer 102, and the gateelectrode 104 is formed on the hybrid organic/inorganic dielectric layer103. The Si/SiO₂ core/shell nanostructures 105 are located on thesurface of the substrate 101. The charge trapping layer 102 comprises amonolayer of the Si/SiO₂ core/shell nanostructures 105. The hybridorganic/inorganic dielectric layer 103 comprises the same material asthe hybrid organic/inorganic dielectric material 106. Typical gatestacks for traditional floating gate transistor include substrate/tunnellayer/charge trapping layer/control layer/gate electrode as shown inFIG. 1B [2, 3, 4, 5]. Normally, very thin oxide as tunnel layer forflash memory transistors must be fabricated by high temperature and/or,slow vacuum process [2, 5]. The present invention didn't involveseparate fabrication of tunnel layer and it significantly simplifies thefabrication of flash gate transistors.

Preferably, the size of Si/SiO₂ core/shell nanostructures is in a rangeof 10 nm to 50 nm, and the thickness of the charge trapping layer is ina range of 10 nm to 50 nm since the trapping points are formed into amonolayer coating. The charge trapping layer comprises a density of thenanostructures in a range of 1×10¹⁰ cm⁻² to 1×10¹² cm⁻². The SiO₂ shellwith thickness of 3 nm to 5 nm functions as a tunnel layer in flashmemory device in the present invention. Preferably, the thickness of theSiO₂ shell is 5 nm. The thickness of the dielectric layer is in a rangeof 300 nm to 800 nm.

FIG. 2 shows a flow chart of a method for fabricating of a non-volatilememory device according to an embodiment of the presently claimedinvention. In step 201, a substrate is provided. In step 202, a Si/SiO₂core/shell nanostructure solution is prepared. In step 203, the Si/SiO₂core/shell nanostructure solution is coated on the substrate. In step204, the Si/SiO₂ core/shell nanostructure solution is dried to form acharge trapping layer. In step 205, a hybrid organic/inorganicdielectric solution is prepared. In step 206, the hybridorganic/inorganic dielectric solution is coated on the charge trappinglayer. In step 207, the hybrid organic/inorganic dielectric solution iscured to form a hybrid organic/inorganic dielectric layer with UV curingand thermal curing. In step 208, a gate electrode is attached on thedielectric layer.

The Si/SiO₂ core/shell nanostructure solution is prepared by mixing Sinanoparticles with ethanol and hydrogen peroxide. The average size ofthe Si nanoparticles is below 30 nm. This size (˜30 nm) of NPs is ableto be obtained with significantly higher production yield than quantumsizes of 1 nm to 5 nm. Also as proved in the present invention, 30nm-NPs can form effective charge-trapping layer for non-volatile memory.Larger NPs (>50 nm) will challenge the film quality of followed hybriddielectrics. The Si/SiO₂ core/shell nanostructure solution is coated onthe substrate by dipping. The nanostructure solution can also be coatedon the substrate by other methods, such as spray, doctor-blade, inkjetprinting, or spin coating. Preferably, these nanostructures are coatedon the substrate to form a monolayer for reducing charge leakage.

Preferably, the weight ratio of Si particles in the nanostructuresolution may be in the range of 1% to 10%, dependent on what coatingmethod is used. The solvents of Si NPs solution can include but notlimited to Isopropanol, n-Propanol, Ethanol, Methanol, Acetone, etc. Avolume ratio of H₂O₂ to the solvents is in the range of 5% to 20%.

The hybrid organic/inorganic dielectric solution is prepared by mixing3-methacryloxypropyltrimethoxysilane (MEMO), zirconium propoxide (ZrPO)and methacrylic acid (MAA). The ratio of MEMO:ZrPO is related to hybridcomposites of organics versus inorganics, preferred to be in the rangeof 7:3 or 6:4, to 5:5. The photoinitiator is added for UV curing toreduce the curing temperature for thermal curing to below 180° C. forhigh-quality hybrid dielectric layer.

The hybrid organic-inorganic dielectric solution is coated on the chargetrapping layer by dip-coating, and then cured by UV and thermal curingat low temperature of 130° C. to 180° C. The sol-gel solution can alsobe coated on the charge trapping layer by other methods, such as spray,doctor-blade, inkjet printing, or spin coating.

UV curing is critical to fabricate high-quality hybrid dielectrics forfloating gate memory. UV curing followed by low-temperature thermalcuring will efficiently remove the fixed-charge defects inas-synthesized hybrid dielectrics. Pre-drying the hybridorganic-inorganic dielectric solution with a pre-drying temperature in arange of 60° C. to 150° C. can be performed before UV curing.

EXAMPLES Example 1

The preferred embodiments for fabrication of Non-Volatile Memory deviceswith Si/SiO₂ core/shell nanostructures as charge trapping layer areshown as below. Lightly-doped silicon wafer with resistivity of 15-25Ohm-cm was selected as substrate and then monolayer Si/SiO₂ core/shellnanostructures were coated as charge trapping layer. Afterwards, 0.5um-1.0 um thick hybrid dielectrics layer was formed by dip coating ascontrol layer. Eventually, top and bottom electrodes were formed byprinting Ag paste. The device area was defined as 2 mm×2 mm.

The organic-inorganic hybrid gate dielectric solution in this inventionis synthesized by using sol-gel reactions between3-methacryloxypropyltrimethoxysilane (MEMO), Zirconium propoxide (ZrPO)and methacrylic acid (MAA). With this organic/inorganic hybrid precursorsolution, high-k dielectric layer can be obtained by dip-coating methodto control the dielectric thickness. After UV curing and thermal curing,current densities passing through hybrid dielectric layers arerelatively low as shown in FIG. 3, where Hybrid 1, 2, and 3 in FIG. 3represent different samples in one batch.

The process flow for Sol-Gel process of hybrid organic/inorganicdielectrics and dip coating is shown in FIG. 4. For example,3-methacryloxypropyltrimethoxysilane (MEMO, 19.5 mmol) was firstpartially hydrolyzed with HCl as a catalyst. The pH value was controlledby HCl to enhance the hydrolysis. 10.5 mmol of each of Zirconiumpropoxide (ZrPO) and methacrylic acid (MAA) were mixed in 5 mL1-propanol. After MEMO was stirred for 30 min, the two solutions weremixed. More DI water was added to facilitate the reaction. The molarratio of MEMO:ZrPO:MAA:water was 6.5:3.5:3.5:18. The solution was sealedand stirred overnight, then added with 1 wt % photo-initiator1-hydroxycyclohexylphenylketone (HCHPK) and diluted with 1-propanol tocontrol the concentration. The solution was filtered with 0.22 umMillipore membrane. Afterwards, the solution was deposited on substrate(PET, glass, or Si wafer) by typical dip coater. Then, the coating wasfirst pre-dried on a hotplate at 110° C. for 30 min. UV curing wasperformed with Dymax Bluewave 200 at 20 mW/cm² for 5 min. Lastly,thermal curing was done in a thermal oven at 170° C. for 3 h.

Si nanoparticles (NPs) can be easily oxidized in an ethanol (EtOH)/H₂O₂solution to form Si/SiO₂ core/shell structures. These nanostructureswith average size of <30 nm were dispersed into ethanol solution andcoated on substrate by dipping. Typical monolayer coating is shown inFIG. 5A under atomic force microscopy (AFM). High-resolutiontransmission electron microscopy (TEM) image in FIG. 5B showed the SiO₂shell is ˜5 nm in thickness.

The memory behavior as shown in FIG. 6 was clearly observed to come frommobile charging/discharging solely related to Si/SiO₂ core/shellnanostructures on the charge trapping layer. Regarding the capacitanceversus voltage (CV) characterization of samples without Sinanostructures, its charge trapping layer didn't show any hysteresis,indicating high-quality hybrid dielectrics without any fixed-chargedefects. The memory window (the width of CV loop) has been tuned viavarying the voltage stress time (FIG. 7A) and the stress voltageamplitude (FIG. 7B), which offers relatively easy control ability fordifferent flexible electronics applications.

Although nano-floating gate transistor memory based on Si/SiO₂core/shell NPs drives voltage not larger than 10V, memory windowremained 75% after 10⁴ s program/erase (P/E) tests with P/E speed within75 ms as shown in FIG. 8.

Example 2

In order to optimize sol-gel process for high-quality hybrid dielectriclayer, below samples for different hybrid dielectrics were investigatedas shown in Table 1. All samples use the same device structures asExample 1. Loops of capacitance versus voltage (CV) were measured forthese devices under different time of voltage stress at gate. The pulsewidth time of applied voltage stress can change the width of CV loopsduring memory charging/discharging process. However, if there aredominant fixed charge defects in dielectrics, the charging/dischargingprocess of memory devices will be screened and the width of CV loopswill become insensitive to voltage stress time [7].

TABLE 1 Investigation of hybrid dielectrics for nano floating gatememory devices Thermal Samples Formula UV cure Cure 1 MEMO:ZrPO =6.5:3.5 20 mW/cm², 170° C., 3 h 5 min 2 MEMO:ZrPO = 8:2 20 mW/cm², 170°C., 3 h 5 min 3 MEMO:ZrPO = 6.5:3.5 NO 170° C., 3 h 4 TiO₂ NPs dispersedin PMMA NO 170° C., 3 h

Sample 1 is similar to the sample in Example 1 and it is cured by UV 20mW/cm², 5 min followed by thermal curing with 170° C., 3 h. Sample 2incorporates fewer ZrPO into dielectrics and is also cured by 20 mW/cm²,5 min and 170° C., 3 h. From CV loops under different voltage stresstime for both sample 1 (FIG. 9A) and sample 2 (FIG. 9B), loop widthsignificantly increases with longer stress time. This is a typicalcharging/discharging process by trapping layers in memory device. Thereare fewer high-k components of ZrPO in sample 2. So the flat-bandcapacitance of sample 2 is ˜114 pF, a little bit lower than 165 pF ofsample 1.

However, sample 3 without UV curing may indicate some fixed defects indielectrics and it involved some —OH groups with hybrid materials [8].Its CV loops stay insensitive to voltage stress time as shown in FIG.9C. UV light irradiation should be very critical to form good crosslinksat molecular scale between inorganic (high-k) and organic components.Comparing sample 1 with sample 3, the high-intensity UV light mayinhibit the formation of —OH group efficiently. Benefiting from improvedsol-gel formula and more powerful UV light, hybrid dielectrics in Sample1 shows better performance than that case in ref. [8]. Then thishigh-quality hybrid dielectrics can meet stringent requirements fornon-volatile memory devices.

As additional reference, in sample 4 TiO₂ NPs were dispersed into PMMAand fabricated into memory devices as dielectric layer. The evolution ofCV loops under voltage stress time for sample 4 is shown in FIG. 9D.Loop width didn't become sensitive to stress time even though the pulseof 500 ms was applied on gate. There should be strongly fixed-chargedefects in dielectrics of sample 4 and be related to interfacial defectson TiO₂ NPs to PMMA. Inorganic NPs blended in polymer matrix act ascharged centers has been described in [8] and these fixed charges indielectrics will deteriorate charge-trapping-layer for floating gatememory structures.

This hybrid dielectrics of the present invention can also find criticalapplications in other thin-film transistors, or nano floating gatetransistors, or planar floating gate transistors.

These Si/SiO₂ core/shell nanostructures of the present invention canalso act as superior charge trapping points in resistive switchingmemory device (named as memoristor) as in ref. [9].

The foregoing description of the present invention has been provided forthe purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise forms disclosed.Many modifications and variations will be apparent to the practitionerskilled in the art.

The embodiments were chosen and described in order to best explain theprinciples of the invention and its practical application, therebyenabling others skilled in the art to understand the invention forvarious embodiments and with various modifications that are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the following claims and their equivalence.

What is claimed is:
 1. A floating gate memory device, comprising: asubstrate; a charge trapping layer formed on the substrate, wherein thecharge trapping layer comprises a hybrid organic/inorganic dielectricmaterial and silicon/silicon dioxide (Si/SiO₂) core/shellnanostructures, and the Si/SiO₂ core/shell nanostructures are embeddedwithin the hybrid organic/inorganic dielectric material; a hybridorganic/inorganic dielectric layer formed on the charge trapping layer;and a gate electrode formed on the hybrid organic/inorganic layer; andwherein each of the Si/SiO₂ core/shell nanostructures comprises a Sicore enclosed by a SiO₂ shell acting as a tunnel layer for the floatinggate memory device.
 2. The device of claim 1, wherein the Si/SiO₂core/shell nanostructures comprises a size of 10 nm to 50 nm and theSiO₂ shell comprise a thickness of 3 nm to 5 nm.
 3. The device of claim1, wherein the Si/SiO₂ core/shell nanostructures comprises a size of 30nm.
 4. The device of claim 1, wherein the charge trapping layercomprises a density of Si/SiO₂ core/shell nanostructures in a range of1×10¹⁰ cm⁻² to 1×10¹² cm⁻².
 5. The device of claim 1, wherein the chargetrapping layer comprises a thickness in a range of 10 nm to 50 nm. 6.The device of claim 1, wherein the charge trapping layer comprises amonolayer of the Si/SiO₂ core/shell nanostructures.
 7. The device ofclaim 1, wherein the hybrid organic/inorganic layer is formed frommethacryloxypropyltrimethoxysilane, zirconium and methacrylic acid. 8.The device of claim 1, wherein the hybrid organic/inorganic layercomprises a thickness in a range of 300 nm to 800 nm.
 9. A method forfabricating the floating gate memory device of claim 1, comprising:providing a substrate; mixing silicon particles with a solutioncomprising ethanol and hydrogen peroxide (H₂O₂) to form asilicon/silicon dioxide (Si/SiO₂) core/shell nanostructures solution,wherein the silicon particles comprises a size of 10 nm to 50 nm, thesilicon particles comprises a weight ratio of 1% to 10% of the Si/SiO₂core/shell nanostructures solution, and a volume ratio of the ethanol tothe H₂O₂ is in a range of 5% to 20%; coating the Si/SiO₂ core/shellnanostructure solution on the substrate; drying the Si/SiO₂ core/shellnanostructure solution with a drying temperature in a range of 60° C. to80° C. to form a charge trapping layer; mixing3-methacryloxypropyltrimethoxysilane (MEMO), zirconium propoxide (ZrPO),methacrylic acid (MAA), and a photoinitiator to form a hybridorganic/inorganic dielectric solution, wherein a volume ratio of theMEMO to the ZrPO is in a range of 7:3 to 5:5; coating the hybridorganic/inorganic dielectric solution on the charge trapping layer;pre-drying the hybrid organic-inorganic dielectric solution with apre-drying temperature in a range of 60° C. to 150° C.; curing thehybrid organic-inorganic dielectric solution on the charge trappinglayer by UV light; curing the hybrid organic/inorganic dielectricsolution thermally with a curing temperature in a range of 130° C. to180° C. to form a hybrid organic/inorganic layer; and forming a gateelectrode on the hybrid organic/inorganic layer.
 10. A method forfabricating the floating gate memory device of claim 1, comprising:providing a substrate; mixing silicon particles with a solutioncomprising an organic solvent and hydrogen peroxide to form asilicon/silicon dioxide (Si/SiO₂) core/shell nanostructures solution,wherein the silicon particles comprises a size of 10 nm to 50 nm;coating the Si/SiO₂ core/shell nanostructure solution on the substrate;drying the Si/SiO₂ core/shell nanostructure solution with a dryingtemperature in a range of 60° C. to 150° C. to form a charge trappinglayer; mixing 3-methacryloxypropyltrimethoxysilane (MEMO), zirconiumpropoxide (ZrPO), methacrylic acid (MAA), and a photoinitiator to form ahybrid organic/inorganic dielectric solution, coating the hybridorganic/inorganic dielectric solution on the charge trapping layer;curing the hybrid organic-inorganic dielectric solution on the chargetrapping layer by UV light; curing the hybrid organic/inorganicdielectric solution thermally with a curing temperature in a range of130° C. to 180° C. to form a hybrid organic/inorganic layer; and forminga gate electrode on the hybrid organic/inorganic layer.
 11. The methodof claim 10, wherein the silicon particles comprises a size of 30 nm.12. The method of claim 10, wherein the silicon particles comprises aweight ratio of 1% to 10% of the Si/SiO₂ core/shell nanostructuressolution.
 13. The method of claim 10, wherein the organic solvent isisopropanol, n-propanol, ethanol, methanol, or acetone.
 14. The methodof claim 10, wherein a volume ratio of the organic solvent to the H₂O₂is in a range of 5% to 20%.
 15. The method of claim 10, wherein a volumeratio of the MEMO to the ZrPO is in a range of 7:3 to 5:5.
 16. Themethod of claim 10, wherein the drying temperature is in a range of 60°C. to 80° C.
 17. The method of claim 10, wherein the step of mixing theMEMO, the ZrPO, the MAA and the photoinitiator to form the hybridorganic/inorganic dielectric solution further comprises: hydrolyzing theMEMO with hydrochloric acid (HCL) to form a first solution; mixing theZrPO, the MAA and propanol to form a second solution; mixing the firstsolution, the second solution and water to from a third solution; adding1-hydroxycyclohexylphenylketone (HCHPK) as the photoinitiator into thethird solution; and diluting the third solution with the HCHPK with1-propanol.
 18. The method of claim 17, wherein the third solutioncomprises a molar ratio of the MEMO:the ZrPO:the MAA:the water with6.5:3.5:3.5:18.
 19. The method of claim 10, wherein the Si/SiO₂core/shell nanostructure solution is coated on the substrate by dipping,and the hybrid organic/inorganic dielectric solution is coated on thecharge trapping layer by dipping.
 20. The method of claim 10, furthercomprising pre-drying the hybrid organic-inorganic dielectric solutionwith a pre-drying temperature in a range of 60° C. to 150° C. before thestep of curing by UV light.